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precision analog microcontroller, 14 - bit analog i/o with mdio interface, arm cortex - m3 data sheet ADUCM320I features analog input/output multichannel, 14 - bit, 1 msps analog - to - digital converter ( adc ) up to 16 adc input channels 0 v to v ref analog input range fully differential and single - ended modes av dd and iov dd monitor s 12- bit voltage output digital - to - analog converters (vdacs) 8 vdacs with a range of 0 v to 2.5 v or av dd outputs 12- bit current output dacs ( idacs ) 4 idacs with a range of 0 ma to 150 ma outputs voltage comparator microcontroller arm cortex - m3 processor, 32 - bit risc architecture serial wire port supports code download and debug clocking options 80 mhz pll with programmable divider trimmed on - chip oscillator ( 3 %) external 16 mhz crystal option external clock source up to 80 mhz memory 2 128 kb independent f lash/ee memories 10,000 cycle f lash/ee endurance 20- year f lash/ee retention 32 kb sram in circuit reprogrammability via i 2 c on - chip peripherals mdio slave up to 4 mhz 2 i 2 c, 2 spi, uart multiple general - purpose input/output ( gpio ) pins : 3.6 v compliant 7 1.2 v compatible when used for mdio 32- element programmable logic array (pla ) 3 general - purpose timers wake - up timer watchdog timer 16- bit pulse width modulator ( pwm ) power supply rang e: 2.9 v to 3.6 v , and 1.8 v to 2.5 v for idacs flexible operating modes for low power applications package and temperature range 6 mm 6mm , 96 - ball csp_ bga package fully specified for ? 40 c to +85c ambient operation tools low cost quickstart development system full third p arty support applications optical networking rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ADUCM320I* product page quick links last content update: 08/30/2016 comparable parts view a parametric search of comparable parts documentation application notes ? an-1322: aducm320 code execution speed ? an-806: flash programming via i2c?protocol type 5 data sheet ? ADUCM320I: precision analog microcontroller, 14-bit analog i/o with mdio interface, arm cortex-m3 data sheet user guides ? ug-868: ADUCM320I/aducm322/aducm322i reference manual software and systems requirements ? iar ewarm ? keil mdkarm design resources ? ADUCM320I material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADUCM320I engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADUCM320I data sheet rev. 0 | page 2 of 26 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? general description ......................................................................... 4 ? specifications ..................................................................................... 5 ? microcontroller electrical specifications .................................. 5 ? timing specifications ................................................................ 11 ? absolute maximum ratings ..................................................... 17 ? esd caution................................................................................ 17 ? pin configuration and function descriptions ........................... 18 ? typical performance characteristics ........................................... 23 ? applications information .............................................................. 24 ? recommended circuit and component values .................... 24 ? packaging and ordering information ......................................... 26 ? outline dimensions ................................................................... 26 ? ordering guide .......................................................................... 26 ? revision history 8/15revision 0: initial version
data sheet ADUCM320I functional block dia gram memory 2 128kb flash 32kb sram arm cortex-m3 processor mux reset ain0 ain5 ain6 ain15 buf_vref2v5 vdac7 idac0 ADUCM320I pvddx agndx iovddx iogndx general- purpose i/o ports swdio swclk gpio ports uart 2 spi 2 i 2 c ext irqs mdio pla internal channels: temperature, av dd , iov dd 2.5v band gap dma nvic reset system serial wire clock system 32.768khz 16mhz osc 80mhz pll 3 gp timer wd timer w ake-u p timer pwm vdac idac3 14-bit sar adc idac idac compa- rator xtalo xtali eclkin pgnd avddx dgndx pwm0 to pwm6 1.8 v ldo vdac0 vdac 13422-001 f igure 1. rev. 0 | page 3 of 26
ADUCM320I data sheet general description the aducm 320i is a fully integrated single package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 mhz arm ? cortex? - m3 processor and integral flash for code and data. the adc on the a ducm320i provides 14 - bit , 1 msps data acquisition on up to 16 input pins that can be programmed for single - ended or differential operation . the voltage at the idac output pins can also be measured by the adc , which is useful for controlling the power consu mption of the current dacs. a dditionally , chip temperature and supply voltages can be measured. the adc input voltage is 0 v to v ref . a sequencer is provided , whi ch allows a user to select a set of adc channels to be measured in sequence without software in volvement during the sequence. the sequence can optionally repeat automatically at a user selectable rate. up to eight v dacs are provided with output ranges that are programmable to one of two voltage ranges. four i dac sou rces are provided. the output currents are programmable with a ra nge of 0 ma to 150 ma. a low drift band gap reference and voltage comparator completes the analog input peripheral set. t he aducm 320i can be configured so that the digital and a nalog outputs retain their output voltages and currents through a watchd og or software reset sequence. thus , a product can remain functional even while the ADUCM320I is resetting itself. the ADUCM320I has a low power arm cortex - m3 processor and a 32 - bit risc machine that offers up to 100 mips peak performance. also integrated on chip are 2 128 kb f lash/ee memory and 32 kb of sram. the flash comprises two separate 128 kb blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. the ADUCM320I operates from an on - chip oscillator or a 16 mhz external crystal and a pll at 80 mhz. this clock can optionally be divided down to reduce current consumption. additional low power modes can be set via software. in normal operating mode , the ADUCM320I digital core consumes about 300 a per mhz. the device includes an mdio interface capable of operating at up to 4 mhz. the capabilit y to simultaneously execute from one flash block and write/erase the other flash block makes the ADUCM320I ideal for 10g, 40 g , and 100g optical applications. user programming is eased by incorporating ph ya dr an d devadd hardware comparators. in addition , the nonerasable kernel code plus flags in user flash provide assistance by allow ing user code to robustly switch between the two blocks of user flash code and data spaces . the ADUCM320I integrates a range of on - chip peripherals that can be configured under software control , as required in the appli - cation . these peripherals include 1 ua rt, 2 i 2 c , and 2 spi s erial input/output ( i/o ) communication controllers, gpio, 32- e lement programmable logic array, 3 general - purpose timer s , plus a wake - up timer and system watchdog timer. a 16 - bit pwm with seven output channels is also provided. gpio pins on the device power up i n high impedance input mode . in output mode , the software choose s between open - drain mode and push - pull mode. the pull - up resistor s can be disabled and enabled in software. in gpio output mode , the inputs can remain enabled to monitor the pins. the gpio pi ns can also be programmed to handle digital or analog peripheral signals , in which case the pin characteristics are matched to the specific requirement. a large support ecosystem is available for the a rm cortex - m3 processor to ease product development of the ADUCM320I . access is via the arm serial wire debug port (sw - dp). on - chip factory firmware supports in - cir cuit serial download via i 2 c . these features are incorporated into a low cost quickstart ? development system supporting this precision analog microcontroller family. note that throughout this data sheet, multifunction pins, such as vdac0/p5.3, are referred to either by the entire pin name or by a single function of the pin, for example, vdac0, when only that function is relevant. rev. 0 | page 4 of 26
data sheet ADUCM320I specifications microcontroller elec trical specification s av dd ( the voltage applied to the avdd3 and avdd4 pin) = iov ddx ( the voltage applied to the iovddx pins (iovdd0, iovdd1, iovdd2) ) = v dd1 ( the voltage applied to the vdd1 pin) = 2.9 v to 3.6 v (s ee figure 14 ) m ax imum difference between supplies = 0.3 v, v ref = 2.5 v internal reference, f core = 80 mhz, t a = ?40c to +85c, unless otherwise noted . pv ddx ( the voltage applied to the pv ddx pins (pvdd0, pvdd1, pvdd2, pvdd3)) f or idacs = 1.8 v to 2.5 v . power - up sequence must be vdd1, iovdd x , av dd x, and then pvdd x, but no dela ys in the sequence are required . table 1. parameter symbol min typ max unit test conditions/comments adc basic specifications s ingle - ended mode , unless otherwise stated adc power - up time 5 s data rate f sample 1 ms ps dc accuracy 1 14 b its 1 lsb = 2.5 v/2 14 resolution 1 16 b its number of data bits integral nonlinearity inl 1 . 75 ls b 2.5 v internal reference ; 1 lsb = 2.5 v/2 14 1.75 ls b 2.5 v external reference ; 1 lsb = 2.5 v/2 14 differential nonlinearity dnl ?0.99 0.75 +1 lsb 2.5 v internal reference ; 1 lsb = 2.5 v/2 14 0.75 ls b 2.5 v external reference ; 1 lsb = 2.5 v/2 14 dc code distribution 3 ls b adc input 1.25 v ; 1 lsb = 2.5 v/ 2 14 adc endpoint errors offset error input buffer off 200 v drift 1 ? 2. 25 + 1. 2 v/c using 2.5 v external reference input buffer on ? 250 v drift 1 ? 2. 6 +2 v/c using 2.5 v external reference match 1 ls b matching compared to ain8 full - scale error input buffer off 400 v gain drift 1 ? 4 + 2 v /c full - scale error drift minus offset error drift input buffer on ? 350 v gain drift 1 ? 4. 5 +3 v / c full - scale error drift minus offset error drift match 1 ls b adc dynamic performance f in = 665.25 hz sine wave, f sample = 100 ksps; input filter = 15 ?, 2 nf signal -to - noise ratio snr i ncludes distortion and noise components input buffer disabled 80 db enabled 74 db total harmonic distortion thd input buffer disabled ? 86 db enabled ? 83 db peak harmonic or spurious noise ? 88 db channel - to - channel crosstalk ? 90 db m easured on adjacent channels rev. 0 | page 5 of 26
ADUCM320I data sheet parameter symbol min typ max unit test conditions/comments adc input i nput buffer not enabled input voltage ranges single - ended mode 1 ag nd4 v ref differential mode 1 ?v ref +v ref v voltage between differential pins compliance 1 ag nd4 av dd4 common mode 1 0. 9 1. 6 v leakage current ain0 to ain4, ain6 to ain15 1.5 na ain5 20 na p in shared with comparator input current 9 a/v at 1 msps; buffer off 6 a /v 800 ksps; buffer off 4 a /v 500 ksps; buffer off; adccnvc[25:16] = 0x1e input capacitance 20 pf du ring adc acquisition adc input buffer 2 w hen enabled by software voltage compliance 1 0. 15 2. 5 v reduced accuracy below 0.15 v input current 100 na v in = 0.15 v to 2.5 v, adc converting on - chip voltage reference 2. 51 v 0. 47 f from vref_1v2 to agnd4; reference is measured with all adcs, vdacs, and idacs enabled accuracy 5 mv t a = 25c reference temperature coefficient 1 ? 34 ?15 +4 ppm/c power supply rejection ratio psrr 60 db internal v ref power - on time 50 ms external reference input range 1 1. 8 2. 5 v adc input current 200 a buffered reffernce output output voltage 2. 504 v accuracy 8 mv t a = 25c, load = 1.2 ma reference temperature coefficient 1 ? 55 ?5 +40 v/c 100 nf from buf_vref2v5 to agnd4 output impedance 10 ? t a = 25c load current 1 1. 2 ma vdac channel specifications r l = 5 k?, c l = 100 pf 3 dc accuracy 1 12 b its 1 lsb = 2.5 v/2 12 resolution 1 12 b its number of data bits relative accuracy 4 inl 4 ls b 1 lsb = 2.5 v/2 12 differential nonlinearity 4 dnl ?0.99 +1 ls b g uaranteed monotonic, 1 lsb = 2.5 v/2 12 offset error 3 15 mv 2.5 v internal reference, dac output code 0 drift 13 v/c gain error 5 0.3 0.85 % 0 v to internal v ref range 0.4 1 % 0 v to av dd range drift 6. 5 ppm /c excluding reference drift mismatch 0. 1 % % of full scale on dac0 rev. 0 | page 6 of 26
data sheet ADUCM320I parameter symbol min typ max unit test conditions/comments analog outputs output voltage range 1 1 0. 15 2. 5 v output voltage range 2 1 0. 15 av ddx ? 0.15 v output impedance 2 ? dac ac characteristics output settling time 10 s s ettled to 1 lsb glitch energy 20 nv - sec 1 lsb change when the maximum number of bits changes simultaneously in the dacxdat register idac channel specifications resolution 1 14 b its combination of overlapping 11 bits and 5 bits full - scale output 1 150 ma supply voltage each channel 1 1. 8 2. 5 v separate pv ddx supply for each channel output compliance range idac0, idac1 0. 4 pv ddx C 0.4 v see figure 11 idac2, idac3 0.4 pv ddx C 0.25 v see figure 11 full - scale error i dac set to 85% of full scale idac0, idac1 0.75 % 25c to 105c range 3.5 % ?40c to +105c range idac2, idac3 0.75 % ?40c to +105c range full - scale error drift idac0, idac1 i nternal v ref ?40c to +85c 25 a /c 25c to 85c 5 a /c idac2, idac3 2 a /c internal v ref integral nonlinearity inl 3 6 ls b 1 lsb = 150 ma/2 11 differential nonlinearity dnl ?0.99 +1 .5 ls b guaranteed 11 - bit monotonic, 1 lsb = 150 ma/2 11 zero - scale error 50 a zero - scale error drift idac0, idac1 300 n a/c idac2, idac3 800 na/c noise current 2 a i dacxcon[5:2] = 0 pull - down current ? 220 ?165 ?100 a when enabled settling time i dacxcon[5:2] = 0 to 0.1% 100 s 4 ma change from midscale to 1% 50 s 4 ma change from midscale full scale to 0 ma 20 s pu ll - down enabled overheat shutdown 135 c j unction temperature pvdd acpsrr i dacxcon[5:2] = 0 100 hz 51 db 1 khz 45 db 10 khz 25 db 100 khz 10 db rev. 0 | page 7 of 26
ADUCM320I data sheet parameter symbol min typ max unit test conditions/comments comparator input offset voltage 10 mv bias current 1 na voltage range 1 agndx av ddx ? 1.2 v capacitance 7 pf hysteresis 1 8. 5 15 mv w hen enabled in software response time 7 s a fecomp[2:1] = 0 temperature sensor i ndicates die temperature, see figure 9 resolution 0. 5 c w hen precision calibrated by the user 6 accuracy 1 1. 34 1. 43 v adc measured voltage for temperature senso r channel without calibration, t a = 25 c power - on reset por 2. 85 2.9 v pin reset mi nimum time to reset 1. 2 s max imum time not to reset 0.5 s watchdog timer wdt timeout period 32 sec default at power - up flash/ee memory endurance 1 10, 000 c ycles data retention 1 20 y ears t j = 85c digital inputs input leakage current logic 1 gpio 1 na v ih = io v dd , pull - up resistor disabled logic 0 gpio 10 na v il = 0 v, pull - up resistor disabled prtaddrx, mck 1 a pu ll - up disabled 16 a pu ll - up to 1.8 v enabled input capacitance 10 pf mck, prtaddrx 6. 5 pf mdio 8. 5 pf xtali 5 pf xtalo 5 pf all other pins 10 pf logic inputs gpio input voltage low v inl 0. 25 iov ddx v high v inh 0.58 iov ddx v mdio prtaddrx input voltage low v inl 0. 36 v high v inh 0.84 v mck, mdio input voltage setup time 10 ns; hold time 10 ns; mck/mdio low v inl 0. 36 v high v inh 0.84 v rev. 0 | page 8 of 26
data sheet ADUCM320I parameter symbol min typ max unit test conditions/comments xtali input voltage low v inl 1. 1 v high v inh 1. 7 v pull - up current 30 120 a v in = 0 v, see figure 10 pull - down current 30 100 a v in = 3.3 v, see figure 10 logic outputs a ll digital outputs excluding xtalo gpio output voltage 7 high v oh iov ddx ? 0.4 v i source = 2 m a low v ol 0. 4 v i sink = 2 ma gpio short - circuit current 1 11 ma s ee figure 13 mdio output voltage high v oh 1.0 v i source = 4 m a low v ol 0. 2 v i sink = 4 m a delay time 100 ns mc k to mdio out oscillators internal system oscillator 16 mh z accuracy 0.5 3 % system pll 80 mh z main system clock external crystal oscillator 16 mh z can be selected in place of internal oscillator 32 khz internal oscillator 32. 768 kh z use for watchdog accuracy 5 20 % external clock 0. 05 80 mh z can be selected in place of pll start - up time p rocessor clock = 80 mhz at power - on 40 ms p or to first user code execution after other reset 1. 5 ms reset to first user code execution from all power - down modes 1.25 s programmable logic array pla propagation delay pin 17 ns f rom input pin to output pin element 1. 5 ns p er pla cell external interrupts pulse width 1 level triggered 7 ns edge triggered 1 ns power requirements 8 power supply voltage range avddx to agndx and iovddx to dgndx 1 2. 9 3.3 3.6 v analog power supply currents avddx current 6. 3 ma a nalog peripherals in idle mode digital power supply current iovddx current in normal mode 4 ma a ll gpio pull - up resistors enabled rev. 0 | page 9 of 26
ADUCM320I data sheet parameter symbol min typ max unit test conditions/comments vddx current normal mode 29 ma c d = 0 (80 mhz clock) executing typical code 20 ma c d = 1 executing typical code 10 ma c d = 7 executing typical code core_sleep mode 16 ma sys_sleep mode 8 ma hibernate mode 6. 6 ma additional power supply currents adc 4. 1 ma c ontinuously converting at 100 ksps adc input buffer 4. 0 ma b oth buffers enabled idac 16. 5 ma e xcluding load current dac 340 a p er powered up dac, excluding load current total supply current 35 40 45 ma v dd1, iovddx, avddx connected together; condition when entering user code: peripheral clocks on, peripherals idle, no load currents thermal performance impedance , junction to ambient 45 c /w jedec 2s2p 1 these numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 enabling the input buffer changes the adc input characteristic s as described in these specifications (the adc input buffer specifications) . 3 the data in the microcontroller electrical specifications section also applies for a load of r l = 1 k? and c l = 100 pf to ground but only f or 0 v to 2.5 v. however, this is not production tested. 4 dac l inearity is calculated using a reduced code range of 100 to 3900. 5 dac gain error is calculated using a reduc ed code range of 100 to an internal 2.5 v v ref . 6 due to self heating , intern al temperature measurements cannot be used to predict external temperatures. this value is only relevant after user calibration and only for internal and external conditions ident ical to those at calibration. 7 the average current from all gpio pins must not exceed 3 ma per pin. 8 power specifcations exclude any load currents to external circuits. rev. 0 | page 10 of 26
data sheet ADUCM320I timing specification s i 2 c timing table 2. i 2 c timing in standard mode (100 khz) s lave parameter description min typ max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.0 s t dsu data setup time 250 ns t dhd data hold time (sda held internally for 300 ns after falling edge of scl) 0 3. 45 s t rsu setup time for repeated start 4.7 s t psu stop condition setup time 4.0 s t buf bus - free time between a stop condition and a start condition 4.7 s t r rise time for both s cl and sda 1 s t f fall time for both s cl and sda 15 300 ns t vd; dat data valid time 3. 45 s t vd;ack data valid acknowledge time 3. 45 s t able 3 . i 2 c timing in fast mode (400 khz) s lave parameter description min typ max unit t l scl low pulse width 1.3 s t h scl high pulse width 0.6 ns t shd start condition hold time 0.6 s t dsu data setup time 100 ns t dhd data hold time (sda held internally for 300 ns after falling edge of scl) 0 s t rsu setup time for repeated start 0.6 s t psu stop condition setup time 0.6 s t buf bus - free time between a stop condition and a start condition 1.3 s t r rise time for both scl and sda 20 300 ns t f fall time for both scl and sda 15 300 ns t vd; dat data valid time 0.9 s t vd; ack data valid acknowledge time 0. 9 s sda (i/o) msb lsb ack msb 1 9 8 2?7 1 scl (i) p s start condition repeated start stop condition s(r) t dsu t h t l t shd t psu t dsu t buf t dhd t vd; dat t vd; ack t r t f t f t r t dhd t rsu 13422-002 f igure 2. i 2 c- compatible interface timing rev. 0 | page 11 of 26
ADUCM320I data sheet spi timing table 4. spi master mode timing (phase mode = 1) parameter description min typ max unit t sl sclk low pulse width ( spidiv + 1) t hclk /2 ns t sh sclk high pulse width ( spidiv + 1) t hclk /2 ns t dav data output valid after sclk edge 0 3 ns t dsu data input setup time before sclk edge ? s clk ns t dhd data input hold time after sclk edge s clk ns t df data output fall time s clk ns t dr data output rise time 25 ns t sr sclk rise time 25 ns t sf sclk fall time 20 ns sclk (polarity = 0) sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t sl t sr t sf t dr t df t dav t dsu t dhd 13422-003 f igure 3. spi master mode timing (phase mode = 1) rev. 0 | page 12 of 26
data sheet ADUCM320I table 5 . spi master mode timing (phase mode = 0) parameter description min typ max unit t sl sclk low pulse width ( spidiv + 1) t hclk /2 ns t sh sclk high pulse width ( spidiv + 1) t hclk /2 ns t dav data output valid after sclk edge 0 3 ns t dosu data output setup before sclk edge ? s clk ns t dsu data input setup time before sclk edge s clk ns t dhd data input hold time after sclk edge s clk ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 20 ns t sf sclk fall time 20 ns sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t dr t df t dav t dosu t dsu t dhd 13422-004 f igure 4 . spi master mode timing (phase mode = 0) rev. 0 | page 13 of 26
ADUCM320I data sheet table 6 . spi slave mode timing (phase mode = 1) parameter description min typ max unit t cs cs to sclk edge 10 ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width ( spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t sfs cs high after sclk edge 20 ns sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs 13422-005 f igure 5 . spi slave mode timing (phase mode = 1) rev. 0 | page 14 of 26
data sheet ADUCM320I table 7 . spi slave mode timing (phase mode = 0) parameter description min typ max unit t cs cs to sclk edge 10 ns t sl sclk low pulse width (spidiv + 1) t hclk ns t sh sclk high pulse width ( spidiv + 1) t hclk ns t dav data output valid after sclk edge 20 ns t dsu data input setup time before sclk edge 10 ns t dhd data input hold time after sclk edge 10 ns t df data output fall time 25 ns t dr data output rise time 25 ns t sr sclk rise time 1 ns t sf sclk fall time 1 ns t docs data output valid after cs edge 20 ns t sfs cs high after sclk edge 10 ns sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso mosi msb in bit 6 to bit 1 lsb in t dhd t dsu msb bit 6 to bit 1 lsb t docs t dav t dr t df t cs 13422-006 f igure 6 . spi slave mode timing (phase mode = 0) rev. 0 | page 15 of 26
ADUCM320I data sheet table 8 . mdio vs mck timing parameter description min typ max unit t setup mdio setup before mck edge 10 ns t hold mdio valid after mck edge 10 ns t delay data output after mck edge 100 ns mck v ih v il v ih v il v oh v ol cfp input mdio cfp input mdio cfp output t setup t hold t delay 13422-007 f igure 7. mdio timing rev. 0 | page 16 of 26
data sheet ADUCM320I absolute maximum rat ings all requirements appli cable to each pin must be met. where multiple limits apply to a pin each one must be met individually. the limits apply according to the functionality of the pins at the time. pins that can be either analog or digital, that is, that have two types indi cated in the pin descriptions, must meet the limits for both types. for pin types , see table 10. when powered up , all ground pins and adc _ refn must be connected together to a node referred to as gnd in table 9 . the limits that are listed must be reduced by any difference between any gndx pin . also, av dd3 must be connected to av dd4 and iovdd1 must be connected to iovdd3 . table 9. parameter rating any pin to gnd ? 0.3 v to + 3.9 v any pvddx pin to gnd ?0.3 v to +2.8 v mdio 1 , mck , and prtaddr0 to prtaddr 4 in mdio mode to gnd ? 0.3 v to +2.1 v between a ny of avddx, iovdd x , and vdd1 pins ? 0.3 v to + 0.3 v any type i p in to gnd 2 ? 0.3 v to iovdd x + 0.3 v any type ai or ao p in to gnd 3 ? 0.3 v to avdd x + 0.3 v any idac x , cdamp x , idac _ tst, iref to gnd ? 0.3 v to pvdd x + 0.3 v adc _ refp to gnd ? 0.3 v to avdd x + 0.3 v total p ositive gpio pin currents 0 ma to 30 ma total n egative gpio pin currents ? 30 ma to 0 ma maximum power dissipation 1 w operating ambient temperature range ? 40c to + 85c storage t emperature range ? 65c to + 160c operating junction temperature range ? 40c to + 120c esd hbm 4 kv esd ficdm 1 kv 1 note t hat t his pin is always in mdio mode. 2 this limit does not apply if no current can be drawn by external circuits on iovddx because, in this case, iov dd follow s to a suitable level. 3 this limit does not apply if no current can be drawn by external circuits on avddx because, in this case, av dd follow s to a suitable level. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution rev. 0 | page 17 of 26
ADUCM320I data sheet pin configuration and function descripti ons 1 a b c d e f g h j k l 2 3 4 5 6 7 8 9 10 11 idac_ tst id ac 0 i dac 2 iovdd1 digi tal i og nd 1 p3.3/ prt ad dr3/ plai[15] p0. 0/ sclk0/ plai[0] cda mp 0 cda mp2 c da mp3 c da mp1 i da c1 iref i dac 3 pgn d dg nd 2 swclk ain 15 / p4.7 ain 14 / p4.6 ain12/ p4.4 ain1 1/ buf_ vref 2v 5 ain10 ain7 ain2 ain1 ain0 ag nd 1 vdac 4 vdac 7/ p5.2 vdac 6/ p5.1 xtali iovdd3 i og nd 3 vdac3 / p5.0 v da c1 v dd 1 av dd 3 ag nd 2 ag nd 3 ain3 ain4 ain6 ain5 ai n9 / p4.3 ai n8 / p4.2 vdac0/ p5.3 vd ac2 / p3.7 / plao[ 29 ] vdac5 dgnd1 ag nd 4 ain13 / p4.5 av dd 4 swdio i og nd 2 iov dd 2 pgn d pv dd 0 1ddvp 3dd vp 2dd vp res et p1.0/sin/ ecl kin/ pla i[4 ] p1. 2/ pwm0/ plai[6] p1.1/sout/ pl ac l k1 / pl ai[ 5] p2.4 /i rq 5/ ad cconv/ pwm6/ plao[ 18 ] p1. 3/ pwm 1/ pl ai[ 7] p1.4/ pwm 2/ scl k1 / pl ao[ 10 ] p1.5/ pwm3/ mis o1/ pla o[ 11] p1.6/ pwm4/ mo si1 / pl ao[ 12 ] p1. 7 /i rq 1/ pwm5/ cs1/ pl ao[ 13 ] p2. 0/i rq 2/ pwm tr ip/ pl ac lk 2/ plai[8] p2. 2/ ir q4/ po r/ clkou t/ plai[ 10 ] p2.3/b m p0.2/ mosi0/ plai[2] p0.5 / s da0 / plao[3] p2.6/ irq7/ plao[2 0] p0 .7/ s da 1/ plao [5] p0 .6/ scl1/ plao[4 ] p3.0/ prt ad dr0/ plai[12] p3.1/ prt ad dr1/ plai[13] p2.7/ irq8 / plao[2 1] p3.5/ m ck / plao [27] xtalo mdio p0 .4/ scl0/ plao[2] p0.3/ irq0/cs0/ placlk0/ plai[3] p0. 1/ miso0/ plai[1] p3.2/ prt ad dr2/ plai[14] p3. 4/ prt ad dr4/ plao[26] av dd _ reg0 av dd _ re g1 vre f_1v2 adc _ refp adc _ refn dvdd_ 2v5 dvd d_1v8 ADUCM320I to p view (not to s ca le) idac analog 13422-008 f igure 8 . pin configuration table 10 . pin function description s pin no. mnemonic type 1 description b2 reset i reset input (active low). an internal pull - up resistor is included. c2 p0.0/sclk0/plai[0] i/o digital i / o port 0.0 (p0.0). s pi0 clock (sclk0). i nput to pla element 0 (plai[0]). d2 p0.1/miso0/plai[1] i/o digital i / o port 0.1 (p0.1). s pi0 master in put , slave out put (miso0). i nput to pla element 1 (plai[1]). d1 p0.2/mosi0/plai[2] i/o digital i / o port 0.2 (p0.2). s pi0 master output , slave input (mosi0). i nput to pla element 2 (plai[2]). e3 p0.3/irq0/cs0/placlk0/plai[3] i/o digital i / o port 0.3 (p0.3). external inter r upt 0 (irq0). sp i0 chip select 0 (cs0) . when using spi0 , configure this pin as cs0. p la clock 0 (placlk0). i nput to pla element 3 (plai[3]). e2 p0.4/scl0/plao[2] i/o digital i / o port 0.4 (p0.4). i 2 c0 serial clock (scl0). o utput of pla element 2 (plao[2]). rev. 0 | page 18 of 26
data sheet ADUCM320I pin no. mnemonic type 1 description e1 p0.5/sda0/plao[3] i/o digital i / o port 0.5 (p0.5). i 2 c0 serial data (sda0). o utput of pla element 3 (plao[3]). f3 p0.6/scl1/plao[4] i/o digital i / o port 0.6 (p0.6) . i 2 c1 serial clock (scl1) . o utput of pla element 4 (plao[4]) . f2 p0.7/sda1/plao[5] i/o digital i / o port 0.7 (p0.7) . i 2 c1 serial data (sda1) . o utput of pla element 5 (plao[5]) . b9 p1.0/ sin/eclkin/plai[4] i/o digital i / o port 1.0 (p1.0) . ua rt i nput (sin) . e xternal input clock (eclkin) . i nput to pla element 4 (plai[4]) . b10 p1.1/sout/placlk1/ plai[5] i/o digital i / o port 1.1 (p1.1) . u art output (sout) p la clock 1(placlk1) . i nput to pla element 5 (plai[5]) . b11 p1.2/pwm0/ plai[6] i/o digital i / o port 1.2 (p1.2) . p wm output 0 (pwm0) . i nput to pla element 6 (plai[6]) . c6 p1.3/pwm1/plai[7] i/o digital i / o port 1.3 (p1.3) . pwm output 1 (pwm1) . i nput to pla element 7 (plai[7]) . c7 p1.4/pwm2/sclk1/plao[10] i/o digital i / o port 1.4 (p1.4) . p wm output 2 (pwm2) . s pi1 c lock (sclk1) . o utput of pla element 10 (plao[10]) . c8 p1.5/pwm3/miso1/plao[11] i/o digital i / o port 1.5 (p1.5) . p wm output 3 (pwm3) . s pi1 master in put , slave out put (miso1) . o utput of pla element 11 (plao[11]) . c9 p1.6/pwm4/mosi1/plao[12] i/o digital i / o port 1.6 (p1.6) . pwm output 4 (pwm4) . s pi1 master out put , slave input (mosi1) . o utput of pla e lement 12 (plao[12]) . c10 p1.7/irq1/pwm5/cs1/plao[13] i/o digital i / o port 1.7 (p1.7) . e xternal inter r upt 1 (irq1) . p wm output 5 (pwm5) . s pi1 chip select 1 (cs1) . when using spi1, configure this pin as cs1 . o utput of pla element 13 (plao[13]) . c5 p2.0/irq2/pwmtrip/placlk2/plai[8] i/o digital i / o port 2.0 (p2.0) . e xternal inter r upt 2 (irq2) . p wm trip (pwmtrip) . p la input clock 2 (placlk2) . i nput to pla element 8 (plai[8]) . c4 p2.2/irq4/ por /clkout /plai[10] i/o digital i / o port 2.2 (p2.2) . e xternal inter r upt 4 (irq4) . r eset out put ( por ). c lock output ( clkout) . i nput to pla element 10 (plai[10]) . rev. 0 | page 19 of 26
ADUCM320I data sheet pin no. mnemonic type 1 description c3 p2.3/bm i/o digital i/o port 2.3 (p2.3) . b oot mode (bm). this pin determines the start - up sequence after every reset. pull - up is enabled at power - up. d9 p2.4/irq5/adcconv/pwm6/plao[18] i/o digital i/o port 2.4 (p2.4) . e xternal inter r upt 5 (irq5) . e xternal i nput to s tart adc c onversions (adcconv) . p wm output 6 (pwm6) . o utput of pla element 18 (pla o [18]) . f1 p2.6/irq7/plao[20] i/o digital i/o port 2.6 (p2.6) . e xternal inter r upt 7 (irq7) . output of pla element 20 (pla o [20]) . g1 p2.7/irq8/plao[21] i/o digital i/o port 2.7 (p2.7) . e xternal inter r upt 8 (irq8) . o utput of pla element 21 (pla o [21]) . g3 p3.0/prtaddr0/plai[12] i/o digital i/o port 3.0 (p3.0) . m dio port address bit 0 (prtaddr0). see the digital inputs parameter in table 1 for details. i nput to pla element 12 (plai[12]) . g2 p3.1/prtaddr1/plai[13] i/o digital i/o port 3.1 (p3.1) . m dio port address bit 1 (prtaddr1) . see the digital inputs parameter in table 1 for details. input to pla element 13 (plai[13]) . d3 p3.2/prtaddr2/plai[14] i/o digital i/o port 3.2 (p3.2) . m dio port address bit 2 (prtaddr2) . see the digital inputs parameter in table 1 for details. i nput to pla element 14 (plai[14]) . b3 p3.3/prtaddr3/plai[15] i/o digital i/o port 3.3 (p3.3) . md io port address bit 3 (prtaddr3) . see the digital inputs parameter in table 1 for details. i nput of pla element 15 (plai[15]) . c11 p3.4/prtaddr4/plao[26] i/o digital i/o port 3.4 (p3.4) . m dio port address bit 4 (prtaddr4) . see the digital inputs parameter in table 1 for details. o utput of pla element 26 (plao[26]) . h1 p3.5/mck/plao[27] i/o digital i/o port 3.5 (p3.5) . md io clock (mck) see the digital inputs parameter in table 1 for more details. output of pla element 27 (plao[27]) . h3 mdio i/o mdio data . e9 swclk i serial wire debug c lock. e10 swdio i/o serial wire bidirectional data . f11 vref_1v2 s 1.2 v reference. this pin c annot be used to source current externally. connect vref_1v2 to agnd x via a 470 nf cap acitor . a11 iref ai idac r eference c urrent. this pin generates the reference current for the idacs and is s et by an external resistor , r ext . connect r ext from iref to agnd4. j6 ain0 ai analog input 0 . j7 ain1 ai analog input 1 . j8 ain2 ai analog input 2 . k8 ain3 ai analog input 3 . l8 ain4 ai analog input 4. l9 ain5 ai analog input 5. ain5 c an be the negati ve input for the comparator. k9 ain6 ai analog input 6. ain6 is also the positi ve input for the comparator. j9 ain7 ai analog input 7. rev. 0 | page 20 of 26
data sheet ADUCM320I pin no. mnemonic type 1 description l10 ain8/p4.2 ai/i/o analog input 8 (ain8) . d igital i/o port 4.2 (p4.2). k10 ain9/p4.3 ai/i/o analog input 9 (ain9) . d igital i/o port 4.3 (p4.3). j10 ain10 ai analog input 10 . j11 ain11/buf_vref2v5 ai/ao analog input 11 (ain11) . b uffered 2.5 v b ias (buf_vref2v5) . the max imum load is 1.2 ma. connect buf_vref2v5 to agnd x via a 100 nf cap acitor. h10 ain12/p4.4 ai/i/o analog input 12 (ain12) . di gital i/o port 4.4 (p4.4) . g10 ain13/p4.5 ai/i/o analog input 13 (ain13) . di gital i/o port 4.5 (p4.5) . h9 ain14/p4.6 ai/i/o analog input 14 (ain14) . di gital i/o port 4.6 (p4.6) . g9 ain15/p4.7 ai/i/o analog input 15 (ain15) . di gital i/o port 4.7 (p4.7) . l5 vdac0/p5.3 ao/i/o voltage dac 0 output (vdac0). di gital i/o port 5.3 (p5.3) . k5 vdac1 ao voltage dac 1 output . l4 vdac2/p3.7/plao[29] ao/i/o voltage dac 2 output (vdac2). di gital i/o port 3.7 (p3.7) . o utput of pla element 29 (plao[29]) . k4 vdac3/p5.0 ao/ i/o voltage dac 3 output (vdac3) . di gital i/o port 5.0 (p5.0) . j4 vdac4 ao v oltage dac 4 output (vdac4). l3 vdac5 ao v oltage dac5 output (vdac5). k3 vdac6/p5.1 ao/i/o v oltage dac 6 output (vdac6). di gital i/o port 5.1 (p5.1) . j3 vdac7/p5.2 ao/i/o voltage dac 7 output (vdac7) . di gital i/o port 5.2 (p5.2) . a2 idac0 ao idac0. 0 ma to 150 ma full - scale output . a3 pvdd0 s power for idac0 . b4 cdamp0 ai damping capacitor 0. connect a damping capacitor from this pin to pvdd0. a10 idac1 ao idac1 . 0 ma to 150 ma full - scale output. a9 pvdd1 s power for idac1 . b8 cdamp1 ai damping capacitor 1. connect a damping capacitor from this pin to pvdd1. a5 idac2 ao idac2 . 0 ma to 150 ma full - scale output. a4 pvdd2 s power for idac2 . b5 cdamp2 ai damping capacitor 2. connect a damping capacitor from this pin to pvdd2. a7 idac3 ao ida c3 . 0 ma to 150 ma full - scale output. a8 pvdd3 s power for idac3 . b7 cdamp3 ai damping capacitor 3. connect a damping capacitor from this pin to pvdd3. b6 pgnd s power supply ground for idacs. a6 pgnd s power supply ground for idacs . a1 idac_tst ai/ao pin for idac test purposes. leave idac_tst unconnected. l2 dvdd_1v8 ao 1.8 v digital supply. a 470 nf capacitor to dgnd1 must be connected to this pin to stabili z e the internal 1.8 v regulator that supplies flash memory and the arm cortex - m3 processor. k2 dvdd_2v5 ao 2.5 v digital supply. a 470 nf capacitor to iognd3 must be connected to this pin to stabili z e the internal 2.5 v regulator that supplies the analog digital control. rev. 0 | page 21 of 26
ADUCM320I data sheet pin no. mnemonic type 1 description f9 avdd_reg0 ao analog regulator 0 supply. a 470 nf capacitor to agnd4 must be connected to this pin to stabili z e the internal 2.5 v regulator that supplies the adc. f10 avdd_reg1 ao analog regulator 1 supply. output of 2.5 v on - chip ldo regulator. a 470 nf capacitor to agnd4 must be connected to this pin. this regulator supplies the idacs. l1 dgnd1 s digital ground 1 for dvdd_1v8. d10 dgnd2 s digital ground 2 . connect to dgnd1. b1 iovdd1 s 3.3 v gpio supply. d11 iovdd2 s 3.3 v gpio supply and interdie communications . j1 iovdd3 s 3.3 v gpio supply. c1 iognd1 s ground for iovdd1 . e11 iognd2 s ground for iovdd2 . k1 iognd3 s ground for iovdd3 and interdie communications . j5 agnd1 s analog g round for vdd1 . k7 agnd2 s esd ground for p ad r ing. l7 agnd3 s ground for avdd3 . h11 agnd4 s ground for avdd4, avdd_reg0 , and avdd_reg1. k6 vdd1 s 3.3 v supply for digital die . l6 avdd3 s vdac and idac supply (3.3 v) . g11 avdd4 s adc supply (3.3 v) . l11 adc_refn ao/a negative decoupling capacitor connection for adc reference buffer . connect this pin to agnd4. k11 adc_refp ao/a positive decoupling capacitor connection for adc reference buffer . connect this pin to a 4.7 f capacitor to the adc_refn pin. adc_refp can be overdriven by an external reference. h2 xtalo o output from the crystal oscillator inverter. when not using an external crystal , leave xtalo unconnected. j2 xtali i input to the crystal oscillator inverter and input to the internal clock generator circuits. when not using an external crystal , connect xtali to dgnd x. 1 i is digital input , o is digital output, s is supply , ai is analog input, and ao is analog output. rev. 0 | page 22 of 26
data sheet ADUCM320I rev. 0 | page 23 of 26 typical performance characteristics 25000 30000 35000 40000 45000 50000 ?60 ?40 ?20 0 20 40 60 80 100 120 adc code (lsb 16) temperature (c) device 1 device 2 device 3 device 4 device 5 13422-009 figure 9. typical temperature measurement (adc code) vs. internal temperature (v dd = 3.3 v, 50 ksps) ?10 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 pin current (a) pin voltage (v) max pull-up min pull-up min pull-down max pull-down 13422-010 figure 10. typical pull-up/pull-down pin current vs. pin voltage (v dd = 3.3 v, 25c) 0 50 100 150 200 250 300 350 0 25 50 75 100 125 150 idac headroom (mv) idac output current (ma) idac2 idac3 idac0 idac1 13422-011 figure 11. typical idac headroom vs. idac output current ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k pvdd ac psrr (db) frequency (hz) idac0 idac1 idac2 idac3 13422-012 figure 12. typical pvdd ac psrr vs. frequency 0 0.5 1.0 1.5 2.0 2.5 3.0 2 6101416 0 4812 output voltage (v) load current (ma) v oh max v oh min v ol min v ol max 13422-013 fig ure 13. typical output voltage vs. load current time (not to scale) 3.6 40ms min vdd1 (v) vdd1 must be above 3v for at least 40ms to complete por after 40ms vdd1 must stay above 2.9v including noise excursions 3.0 2.9 13422-014 fi gure 14. vdd1 power-on requirements
ADUCM320I data sheet applications informa tion recommended c ircuit and c omponent v alues figure 15 shows a typical connection diagram for the ADUCM320I . supplies and regulators must be adequately decoupled with capacitors connected between the avddx, pvddx, dvdd_x, avdd_regx, iovddx, and vdd1 balls and their associated gnd balls (agndx, pgnd, iogndx, and dgndx ). table 10 indicates which ground balls are paired with which supply balls. there are four digital supply balls, iovdd1, iovdd2, iovdd3, and vdd1. decouple these balls with a 100 nf capacitor pla ced as near as possible to each of the four balls and their associated gnd balls (iogndx and agnd1, respectively). in addition, place a 10 f capacitor conveniently near to these balls. similarly, the analog supply pins, avdd3 and avdd4, each require a 10 0 nf capacitor placed as near as possible to each ball and its associated agndx ball, and place a 10 f capacitor conveniently near to these balls. the idacs source their output currents from the pvddx supply balls. each pvddx supply ball must have a 100 n f capacitor near to each ball and their associated gnd balls (pgnd). in addition, place at least one 10 f capacitor at the source of the pvddx supply. the idac output filters depend on a 10 nf capacitor being placed between the cdampx and pvddx pins . the adc reference requires a 4.7 f capacitor placed between adc_refp and adc_refn and located as near as possible to each ball. adc_refn must be connected directly to agnd4. the ADUCM320I contains four internal regulators. these regulators require external decoupling capacitors. the dvdd_1v8 and dvdd_2v5 balls each require a 470 nf capacitor to dgnd1 and iognd3, respectively. avdd_reg0 and avdd_reg1 each require a decoupling capacitor to agnd4. to g enerate an accurate and low drift reference current, connect the iref ball to agnd4 via a low ppm 3.16 k? resistor. take care in the layout to ensure that currents flowing from the ground end of each decoupling capacitor to its associated ground ball share as little track as possible with other ground currents on the printed circuit board. rev. 0 | page 24 of 26
data sheet ADUCM320I g11 l6 b6 pgnd reset reset adc_refp gnd dgnd swdio tx swclk avdd avdd3 avdd4 vref_1v2 iref adc_refn a vdd_reg0 avdd_reg1 agnd1 agnd3 agnd2 f9 l11 k11 a11 f11 h11 l7 k7 j5 f10 agnd4 3.16k ? 0.47f 4.7f 0.47f 0.47f b2 c1 e11 p1.1/sout j2 swdio h2 a3 a9 12pf 10nf a6 pgnd l1 d10 ADUCM320I cdamp2 cdamp1 cdamp0 pvdd3 pvdd2 pvdd1 pvdd0 xtalo xtali reset reset a4 a8 b4 b8 b5 vdd1 cdamp3 b7 swclk p1.0/sin/eclkin/plai[4] p2.3/bm k1 iovdd1 iovdd3 iovdd2 vdd1 dvdd_1v8 dvdd_2v5 dgnd1 dgnd2 iognd1 iognd2 iognd3 10k ? pvdd 10nf 10nf 10nf dvdd vdd1 0.47f 0.47f vdd1 10k ? 10f 10f 0.1f 10k? 1. 6? vin vout en/uvlo gnd dgnd avdd dvdd agnd agnd 0.1f 10f adp7102ardz3.3 0.1f v in sense/adj pg 0.1f 1.6? vdd1 dgnd dgnd1 10f vin vout en gnd adp1741acpz ss ep 10f 30k? 10k? 10f +2.5v 10f adj pvdd 12pf pgnd pgnd pgnd dgnd nc dvdd agnd 0.1f agnd1 l2 k6 j1 d11 b1 k2 e10 b10 e9 b9 c3 interface board connector rx 13422-015 f igure 15 . recommended circuit and component values rev. 0 | page 25 of 26
ADUCM320I data sheet packaging and ordering information outline dimensions 6.10 6.00 sq 5.90 5.00 ref sq 0.35 0.30 0.25 04-02-2013- a coplanarit y 0.08 a b c d e f g h j k l 7 6 3 2 1 5 4 ball diameter 0.50 bsc 0.50 ref de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane 1.200 1.083 1.000 89 1011 compliant t o jedec s t andards mo-195-ac with the exception to ball count. 0.223 nom 0.173 min 0.93 0.86 0.79 f igure 16 . 96 - ball chip scale package ball grid array [csp_bga] (bc- 96 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity aducm320bbczi ? 40 c to +85 c 96- ball chip scale package ball grid array [csp_bga] bc -96 -2 429 aducm320bbczi -rl ? 40c to +85c 96- ball chip scale package ball grid array [csp_bga] bc -96 -2 2,500 ev al -ad u cm320 i qspz e valuation board with quickstart development system 1 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13422 -0- 8/15(0) www.analog.com/ ADUCM320I rev. 0 | page 26 of 26

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